Timing Channels through Shared Hardware Accelerators: Attacks and Protection

Hardware specialization in the form of accelerators offer significant improvement in performance and energy efficiency compared to general-purpose processors. However, there is usually a lack of security guarantees by the existing hardware design methodologies. In this report, we show that shared hardware accelerators are vulnerable to timing channel attacks and can leak sensitive information. We demonstrate a covert channel attack on a real system consisting of a multicore processor and a shared hardware accelerator. We designed a communication protocol which allows two users of an accelerator to send arbitrary messages over the covert channel. To mitigate timing channel attacks, we propose a novel design automation approach that removes interference and allows hardware accelerators to be shared securely. Experimental results show that the proposed approach eliminates timing channels in shared hardware accelerators with small performance and area overhead.